As integrated circuits become faster and denser, requirements for control of topographical features such as planarity, shape, and thickness become increasingly stringent. The necessity for verifying that a given wafer is sufficiently planar and within specifications, i.e. in qualifying and selecting wafers even before processing begins or during processing, is becoming ever greater. A critical component in the characterization of wafers is the wafer topography, sometimes termed substrate geometry. In particular it is necessary to characterize the surface profile in order to determine whether there is perturbation of the profile to the extent that would prevent the wafer from being processed into a finished product. This characterization is particularly critical in the edge regions of semiconductor wafers, where there is generally a slope roll off. In these regions traditional thickness measurements are unlikely to effectively and accurately reveal and characterize such perturbations. Present techniques utilize wafer front & back surface and thickness measurements, which are processed to provide a curvature profile by taking the second derivative of the data curve.